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PCS1P2192A VDP Multiple Pixel Clock Generator
Features
* Generates multiple clock outputs from 20MHz external reference clock * Input frequency: 20MHz * Output frequencies: o Selectable CLKOUT: 108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz, 25MHz, 45MHz, and 40MHz o REFOUT: 20MHz * Operating Supply Voltage: 3.3V 0.3V * Zero ppm frequency synthesis error on all clock outputs * 8-pin SOIC package
Product Description
The PCS1P2192A is a clock generator that generates multiple selectable pixel clock outputs for Video Display Panel applications from an external 20MHz reference clock. The PLL based clock generator is specifically designed to provide zero ppm frequency synthesis error on all clock outputs. Various pixel clock rates are selectable through frequency selection pins S[2:0] (Refer to Frequency Selection Table) The device provides a reference clock output additionally. Operating Supply Voltage for this device is 3.3V 0.3V. The device is available in an 8-pin SOIC package.
Application
PCS1P2192A is targeted towards Video Display Panel (VDP) applications like VGA, SVGA, XGA, WXGA, UXGA.
Block Diagram
VDD
[S2: S0]
CLKIN
PLL
CLKOUT
REFOUT
GND
(c)2010 SCILLC. All rights reserved. JANUARY 2010 - Rev. 2
Publication Order Number: PCS1P2192/D
PCS1P2192A
Pin Configuration
CLKIN 1 GND 2 PCS1P2192A S0 3 S1 4
8 7
VDD CLKOUT REFOUT S2
6 5
Pin Description Pin#
1 2 3 4 5 6 7 8
Pin Name
CLKIN GND S0 S1 S2 REFOUT CLKOUT VDD
Type
I P I I I O O P
Description
20MHz external reference clock input. Ground Connection. Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Reference clock output. Clock output. Device Power Supply .
Frequency Selection Table
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CLKOUT (MHz) 108 27 33.2 85 65 25 45 40
Rev. 2 | Page 2 of 7 | www.onsemi.com
PCS1P2192A
Absolute Maximum Ratings Symbol
VDD, VIN TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Parameter
Rating
-0.5 to +4.6 -65 to +125 260 150 2
Unit
V C C C KV
Voltage on any input pin with respect to Ground
Recommended Operating Conditions Parameter
VDD TA CL CIN Operating Voltage Operating Temperature Load Capacitance Input Capacitance
Description
Min
3.0 0
Typ
3.3
Max
3.6 +85 15 7
Unit
V C pF pF
DC Electrical Characteristics Symbol Parameter
VIL VIH IIL IIH VOL VOH IDD ICC VDD tON ZOUT Input low voltage (For CLKIN) Input high voltage (For CLKIN) Input low current Input high current Output low voltage (VDD = 3.3V, IOL = 8mA) Output high voltage (VDD = 3.3V, IOH = -8mA) Static supply current Operating Voltage Power-up time (first locked cycle after power-up) Output impedance
1
Min
GND-0.3 2.0
Typ
Max
0.8 VDD+0.3 50 -50 0.4
Unit
V V A A V V mA mA V mS
2.4 5 9 3.0 3.3 1 40 3.6
Dynamic supply current (3.3V and no load)
Note: 1. CLKIN pulled low.
Rev. 2 | Page 3 of 7 | www.onsemi.com
PCS1P2192A
AC Electrical Characteristics Symbol
fIN fOUT tLH tHL
1 1
Parameter
Min
Typ
20 108, 27, 33.2, 85, 65, 25, 45, 40
Max
Unit
MHz MHz
Input frequency Output frequency Output rise time (Measured from 20% to 80%) Output fall time (Measured from 80% to 20%) Period Jitter Frequency Synthesis Error (All Outputs) Output duty cycle 40 1.2 0.8
2.5 1.6 150 0 50 60
nS nS pS ppm %
tJC tD
Note: 1. Measured with a capacitive load of 15pF.
Rev. 2 | Page 4 of 7 | www.onsemi.com
PCS1P2192A
Typical Application Schematic
VDD CLKIN
1 CLKIN 2
GND
VDD
8
0.01uF GND
VDD 0 0 0 VDD
CLKOUT 7
3 S0
S1
REF 6 0 S2 5 0
VDD
4
0
Use either pull-up or pull-down 0 Resistor with [S2:S0] for selection of CLKOUT frequencies.
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended. * Dedicated VDD and GND planes. * The device must be isolated from system power supply noise. A 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. * In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the figure below.
As short as possible
VDD GND
Rev. 2 | Page 5 of 7 | www.onsemi.com
PCS1P2192A
Package Information
8-Pin SOIC Package
E
H
D
A2
A
e A 1 B
C L
D
Dimensions Inches Min
A1 A A2 B C D E e H L 0.004 0.053 0.049 0.012 0.007
Symbol
Max
0.010 0.069 0.059 0.020 0.010
Millimeters Min Max
0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25
0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8
Rev. 2 | Page 6 of 7 | www.onsemi.com
PCS1P2192A
Ordering Code Part Number
PCS1P2192AG-08SR
Marking
ACZ
Package Type
8-Pin SOIC, TAPE & REEL, Green
Temperature
0 to +85 C C
A "microdot" placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free.
Licensed under U.S Patent #5,488,627 and #5,631,921
Note: This product utilizes US Patent #6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003. are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes ON Semiconductor and without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. U.S Patent Pending; Timing-Safe and Active Bead are trademarks of PulseCore Semiconductor, a wholly owned subsidiary of ON Semiconductor. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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